April 26, 2012, GSA Silicon Summit, Mountain View, CA—Subramanian Iyer from IBM looked the issues to "Keeping Moore's Law Alive" in his presentation at the Computer History Museum, a fitting place for a technology forecast. From an IDM perspective, the primary questions are: is there a problem, what to do about scaling, and what are the long term outlooks?
Continuing scaling is an issue for the industry, and underlying infrastructure. Scaling is always been a function of the cost of the next generation, and the next node always increases in complexity. Moving forward may be in fact it by the lack of photography solutions, since the cost of the new lithography is currently out of the question.
The cost of new lithography is also driving the increasing complexity, as people develop new workarounds for shortcomings in existing exposure techniques. As a result, scaling the cost per transistor is no longer decreasing by a half in every generation.
Previous processes allow for customization of the process or performance or for power. At the 90nm node, the industry saw a bifurcation where it was no longer possible to continue increasing power. A constant supply voltage power increases exponentially as the number of circuits increases. The alternative is to design for a fixed power budget and still increase the circuits for performance. There are lots of knobs and different trade-offs depending on whether there is a constraint on power or power density.
There is always been problems with scaling and lithography, starting with bipolar transistors. Because of the power problems, the industry developed CMOS, and proceeded with classical Dennard scaling to the 90 nm node. At that point, little graphics scaling did not produce increases in performance, so they introduced strain to increase carrier mobility. Unfortunately, materials engineering is like drugs, withdrawal is very hard.
After strain engineering, industry move to high-K dialectics, and now are adding metal gates. All of these process changes added to process complexity, and there is no clear path going forward. Instead of focusing on process, the industry can continue scaling by looking at orthogonal scaling paths. One area to increase circuit density on chip is changing the nature of on chip memory.
In today's SOC's, memory consumes a very large percentage of the real estate. One way to improve the density is to change from SRAM to embedded DRAM. This change in memory structures offers a one generation change in density. Test is shown that in large caches, the time of flight for large size embedded DRAM is faster than SRAM. The DRAM offers a 3.5 times improvement in area, a five-day times reduction in power and up to 30 times improvement in speed over SRAM.
Another way to change performance is to look at the on chip power delivery, distribution, and dissipation. The deep trench capacitors needed for DRAM can also be used to decouple power supplies. This power decoupling offers up to 10 percent improvement in chip level performance, or equivalent reductions in power consumption. The reason decoupling helps is that it reduces noise and increases margins, thereby reducing guard bands.
Another area for further investigation is process simplification. As the industry transitions to 3-D transistors, one interesting development is that SOI can reduce process complexity. In bulk processes, deep trench capacitors require a thick oxide collar to show off the parasitic transistors, but in SOI, the P well doesn't exist. In addition the EPI handle replaces the N plus implant.
While other areas in circuits and devices need attention, physical scaling continues. Limiting factor for the basic transistor is approximately 25 atoms, which means that 7nm structures are achievable. Scaling beyond 22nm requires alternative device structures.
The first realization of this will be in FINs, then wires, and then something else. These may be carbon nanostructures or quantum devices.
So there experiments are showing that the FINfets have superior performance in SOI process than in bulk. The dielectric isolation eliminates the junction leakage to substrate. FIN height variability is reduced, because the height of the FIN is defined by SOI thickness, and source strain depth is self-limited by the oxide. In comparison, bulk processes are affected by local oxide fill, dummy gate pull, etc., and the source-drain depth profile is another area of variation. SO I is simpler than bulk and results in lower costs and improve performance.
Power is not only a constraint on the chip, but is a key factor in the overall system. Data communications between chips can take up to a third of the system power. On-chip wiring may dissipate between 60 and 80 percent of the power. It now cost more energy to move data at to compute it. Scaling cannot fix this problem, but tighter inter-chip connections can.
Heterogeneous integration into 2.5-D or 3-D structures can improve time to market, increase density and performance, while reducing power, complexity and costs. Systems will still need to scale but 3-D is orthogonal to process changes. 2.5 D systems with interposers are a small partial step that uses older technology, MCM or multichip modules. Integrated 3-D chips will have a lamination of thinned chips with TSVs for interconnects. The TSVs have feature sizes significantly larger than any other feature on chip.
This new type of architecture is becoming necessary as memory scaling issues come up. As feature sizes scale in memories, the performance is not keeping pace. However, stacking memory chips into a cube and adding control logic can improve the performance by the equivalent of two process generations. Stacking die on a silicon substrate requires more than just packaging technology.
The TSV technology facilitates integration of wires, silicon, and even decoupling caps within an interconnection structure. This concept can be applied to all device types, but requires changes in computer and memory architectures take full advantage of all the capabilities.
Ultimately, these increasing levels of performance and integration must be measured against the real competition, the human brain. The whole idea of Von Neumann computing, and a sequential structured flow is computation driven and power agnostic. The human brain, on the other hand, is reconfigurable, fault tolerant, and energy driven and power aware, so computational energy requirements scale with activity. The question we have to ask is, do we have the technology to make this transformation?