April 26, 2012, GSA Silicon Summit, Mountain View, CA—Subramani Kengeri from Global Foundries acknowledged a gap between efforts and capabilities in the lab versus those in the fab. To continue working on Moore's law requires an SOC view and more collaboration.
Currently, four areas are driving improvements in silicon; interconnect, lithography, packaging, and silicon technology evolution. The industry will hit the planar limits in '15 and will run into the atomic limits ay '25. The gap between lab and fab starts at 20 nm.
Everyone agrees that the base device for transistors will be FINs at the 14nm node, and 10nm and below will need substantial innovation. FINfets will be on bulk at 10nm and we may start to see SiGe PMOS FINfets at that node. When we get to 7nm, we may be using III-V materials in place of silicon.
We cannot scale planar beyond 14nm due to issues like oxide limits and the lack of knobs to manage and optimize the bulk materials. The lithography issues prevent scaling channel lengths and voltage scaling cannot track the feature sizes. The power, performance, and cost (PPC) benefits of FINfets at the 14nm node will stop any efforts to develop bulk CMOS.
Planar devices are still capable of getting a 50 percent improvement in PPC, but the FINs will get 2.5 times improvement, greater than one node difference. When these changes are applied to SoCs, the device performance differences translate to lower supply voltage and much loser power. Even at supplies as low as 0.8V, the FIN technology offers higher performance, so the concept of libraries optimized for low power or performance will go away.
The limiting factor for SoC performance will be SRAM performance. Scaling the supply voltage reduces thresholds and sense margins, making the speed and signal-noise ratio the determining factor in memory speeds.
While the device and process issue dominate, the number of starts and tapeouts continues to drop at the smaller nodes. They track ramp times for a new process from 50 to 250 tapeouts. For the 90 and 65 nm nodes, it took three quarters to ramp to 250 designs. The qualifications for 45/40 nm were delayed due to the lack of products to qualify. It appears that the 32/28 node will also have a slow qualification and a slower ramp to high volume.
The time to volume is a complex economic issue, involving fab costs and capacity, development costs, design costs, and others. The increase in complexity in all the areas has increased the cost of scaling from 28 to 20 nm by significant amounts, driven by the costs of lithography.
To bypass the limits of EUV, the optical complexity has increased due to source-mask optimization, double patterning, and other techniques. The EUV costs will be exponentially higher than the last generation of optical lithography tools. Module-based lithography will be expensive, and will require a new middle of line set of processes.
The MOL functions will grow faster than any other area and will change with EUV. The best case scenario indicates that EUV will not be ready for the 14nm node, so the 20nm node might be in place for a long semiconductor production lifetime. Some of the problems for EUV include mask defects, capacity, and production lifetimes. The only way to get to production-ready equipment is to partner.
In the past, major process changes had a lead adopter, like memory, CPU, or GPU. The partner had to cooperate closely with the fab to change the technology and different relationships evolved from the process. Now, the need for partnerships is growing, but the drivers for the next generation are missing.
For example, the 20nm process is technology platform that was scaled from 28nm. The major change was to high-K, metal gate, and the time to volume is still fairly aggressive. Next we will see FINs, after a decade of R&D, that are optimized for mobile SoC designs. The process will offer area and power savings, enable more IP reuse, and will minimize extension risks.
When Moore's law is applied to SoCs the metrics are scale per unit cost, and power increase per node to give a MHz/mW/$ unit of measure. The PPC has to increase by 2x to justify the move to the next node. The alternative is to go to 2.5-D and 3-D packaging to improve memory bandwidth and optimize power consumption.